Some circuit systems may generate and transmit a signal as a balanced pair of signals in order to remove common-mode noise from the signal. In particular configurations, the balanced pair may be a complementary or differential pair of signals.
Each signal in the balanced pair may transition between at least two voltage levels, such as a high voltage level and a low voltage level. Depending on the application, it may be desirable for the timing characteristics of the two signals of the pair to match or be in as close of alignment as possible. One timing characteristic may be duty cycle. That is, it may be desirable for the two signals to have as close to the same duty cycle as possible. Another timing characteristic may be transition time, which is the time that a signal transitions from one voltage level to another voltage level. The difference in time between when two signals perform respective transitions may be referred to as skew.
It may be desirable for two signals to perform respective transitions at the same time or as close to the same time as possible. Otherwise stated, it may be desirable for the two signals to have as little skew between them as possible. Minimum skew may be especially desirable in double date rate (DDR) signaling schemes where information is communicated on both the rising edges and the falling edges of a signal.
Circuit systems that communicate a pair of signals with desirably as little skew as possible may include a de-skew circuit. As performance characteristics for electronic devices continually require higher data rates, reduced power consumption, smaller sizes, and less susceptibility to process, variation, and temperature (PVT) variations, improved de-skew circuits that meet these requirements may be desirable.